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1 ltc1407/ltc1407a 1407f serial 12-bit/14-bit, 3msps simultaneous sampling adcs with shutdown n 3msps sampling adc with two simultaneous differential inputs n 1.5msps throughput per channel n low power dissipation: 14mw (typ) n 3v single supply operation n 2.5v internal bandgap reference with external overdrive n 3-wire serial interface n sleep (10 m w) shutdown mode n nap (3mw) shutdown mode n 80db common mode rejection at 100khz n 0v to 2.5v unipolar input range n tiny 10-lead ms package , ltc and lt are registered trademarks of linear technology corporation. n telecommunications n data acquisition systems n uninterrupted power supplies n multiphase motor control n i & q demodulation n industrial control the ltc ? 1407/ltc1407a are 12-bit/14-bit, 3msps adcs with two 1.5msps simultaneously sampled differential inputs. the devices draw only 4.7ma from a single 3v supply and come in a tiny 10-lead ms package. a sleep shutdown feature lowers power consumption to 10 m w. the combination of speed, low power and tiny package makes the ltc1407/ltc1407a suitable for high speed, portable applications. the ltc1407/ltc1407a contain two separate differential inputs that are sampled simultaneously on the rising edge of the conv signal. these two sampled inputs are then converted at a rate of 1.5msps per channel. the 80db common mode rejection allows users to elimi- nate ground loops and common mode noise by measuring signals differentially from the source. the devices convert 0v to 2.5v unipolar inputs differen- tially. the absolute voltage swing for ch0 + , ch0 C , ch1 + and ch1 C extends from ground to the supply voltage. the serial interface sends out the two conversion results in 32 clocks for compatibility with standard serial interfaces. + 1 2 7 3 6 s & h + 4 5 s & h gnd 11 exposed pad v ref 10 f ch0 ch0 + ch1 ch1 + 3v 10 f ltc1407a 8 10 9 three- state serial output port mux 2.5v reference timing logic v dd sdo conv sck 1407a bd 3msps 14-bit adc 14-bit latch 14-bit latch frequency (mhz) 0.1 ?0 thd, 2nd, 3rd (db) ?4 ?8 ?2 ?6 1 10 100 1407 g02 ?6 ?2 ?8 ?04 ?0 ?4 thd 3rd 2nd features descriptio u applicatio s u block diagra w thd, 2nd and 3rd vs input frequency
2 ltc1407/ltc1407a 1407f (notes 1, 2) supply voltage (v dd ) ................................................. 4v analog input voltage (note 3) ................................... C 0.3v to (v dd + 0.3v) digital input voltage .................... C 0.3v to (v dd + 0.3v) digital output voltage .................. C 0.3v to (v dd + 0.3v) power dissipation .............................................. 100mw operation temperature range ltc1407c/ltc1407ac ............................ 0 c to 70 c ltc1407i/ltc1407ai ......................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number mse part marking ltbdq ltbdr ltafe ltaff LTC1407CMSE ltc1407imse ltc1407acmse ltc1407aimse t jmax = 125 c, q ja = 150 c/ w exposed pad is gnd (pin 11) must be soldered to pcb the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = 3v. ltc1407 ltc1407a parameter conditions min typ max min typ max units resolution (no missing codes) l 12 14 bits integral linearity error (notes 5, 17) l C2 0.25 2 C4 0.5 4 lsb offset error (notes 4, 17) l C10 1 10 C20 220 lsb offset match from ch0 to ch1 (note 17) C5 0.5 5 C10 110 lsb gain error (notes 4, 17) l C30 5 30 C60 10 60 lsb gain match from ch0 to ch1 (note 17) C5 1 5 C10 210 lsb gain tempco internal reference (note 4) 15 15 ppm/ c external reference 1 1 ppm/ c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = 3v. symbol parameter conditions min typ max units v in analog differential input range (notes 3, 9) 2.7v v dd 3.3v 0 to 2.5 v v cm analog common mode + differential 0 to v dd v input range (note 10) i in analog input leakage current l 1 m a c in analog input capacitance 13 pf t acq sample-and-hold acquisition time (note 6) l 39 ns t ap sample-and-hold aperture delay time 1 ns t jitter sample-and-hold aperture delay time jitter 0.3 ps t sk sample-and-hold aperture skew from ch0 to ch1 200 ps cmrr analog input common mode rejection ratio f in = 1mhz, v in = 0v to 3v C60 db f in = 100mhz, v in = 0v to 3v C15 db consult ltc marketing for parts specified with wider operating temperature ranges. absolute axi u rati gs w ww u package/order i for atio uu w co verter characteristics u a alog i put u u 1 2 3 4 5 ch0 + ch0 v ref ch1 + ch1 10 9 8 7 6 conv sck sdo v dd gnd top view 11 mse package 10-lead plastic msop
3 ltc1407/ltc1407a 1407f i ter al refere ce characteristics uu u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = 3v. ltc1407 ltc1407a symbol parameter conditions min typ max min typ max units sinad signal-to-noise plus 100khz input signal 70.5 73.5 db distortion ratio 750khz input signal l 68 70.5 70 73.5 db 100khz input signal, external v ref = 3.3v, v dd 3 3.3v 72.0 76.3 db 750khz input signal, external v ref = 3.3v, v dd 3 3.3v 72.0 76.3 db thd total harmonic 100khz first 5 harmonics C87 C90 db distortion 750khz first 5 harmonics l C83 C77 C86 C80 db sfdr spurious free 100khz input signal C87 C90 db dynamic range 750khz input signal C83 C86 db imd intermodulation 1.25v to 2.5v 1.40mhz into ch0 + , 0v to 1.25v, C82 C82 db distortion 1.56mhz into ch0 C . also applicable to ch1 + and ch1 C code-to-code v ref = 2.5v (note 17) 0.25 1 lsb rms transition noise full power bandwidth v in = 2.5v p-p , sdo = 11585lsb p-p (C3dbfs) (note 15) 50 50 mhz full linear bandwidth s/(n + d) 3 68db 5 5 mhz t a = 25 c. v dd = 3v. parameter conditions min typ max units v ref output voltage i out = 0 2.5 v v ref output tempco 15 ppm/ c v ref line regulation v dd = 2.7v to 3.6v, v ref = 2.5v 600 m v/v v ref output resistance load current = 0.5ma 0.2 w v ref settling time 2ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v. symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.3v l 2.4 v v il low level input voltage v dd = 2.7v l 0.6 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 3v, i out = C 200 m a l 2.5 2.9 v v ol low level output voltage v dd = 2.7v, i out = 160 m a 0.05 v v dd = 2.7v, i out = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d out v out = 0v to v dd l 10 m a c oz hi-z output capacitance d out 1pf i source output short-circuit source current v out = 0v, v dd = 3v 20 ma i sink output short-circuit sink current v out = v dd = 3v 15 ma dy a ic accuracy u w digital i puts a d digital outputs u u
4 ltc1407/ltc1407a 1407f symbol parameter conditions min typ max units f sample(max) maximum sampling frequency per channel l 1.5 mhz (conversion rate) t throughput minimum sampling period (conversion + acquisiton period) l 667 ns t sck clock period (note 16) l 19.6 10000 ns t conv conversion time (note 6) 32 34 sclk cycles t 1 minimum positive or negative sclk pulse width (note 6) 2 ns t 2 conv to sck setup time (notes 6, 10) 3 ns t 3 sck before conv (note 6) 0 ns t 4 minimum positive or negative conv pulse width (note 6) 4 ns t 5 sck to sample mode (note 6) 4 ns t 6 conv to hold mode (notes 6, 11) 1.2 ns t 7 32nd sck - to conv - interval (affects acquisition period) (notes 6, 7, 13) 45 ns t 8 minimum delay from sck to valid bits 0 through 11 (notes 6, 12) 8 ns t 9 sck to hi-z at sdo (notes 6, 12) 6 ns t 10 previous sdo bit remains valid after sck (notes 6, 12) 2 ns t 12 v ref settling time after sleep-to-wake transition (notes 6, 14) 2 ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = 3v. symbol parameter conditions min typ max units v dd supply voltage 2.7 3.6 v i dd supply current active mode, f sample = 1.5msps l 4.7 7.0 ma nap mode l 1.1 1.5 ma sleep mode (ltc1407) 2.0 15 m a sleep mode (ltc1407a) 2.0 10 m a pd power dissipation active mode with sck in fixed state (hi or lo) 12 mw power require e ts w u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v. ti i g characteristics u w note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground gnd. note 3: when these pins are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below gnd or greater than v dd without latchup. note 4: offset and range specifications apply for a single-ended ch0 + or ch1 + input with ch0 C or ch1 C grounded and using the internal 2.5v reference. note 5: integral linearity is tested with an external 2.55v reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. the deviation is measured from the center of quantization band. note 6: guaranteed by design, not subject to test. note 7: recommended operating conditions. note 8: the analog input range is defined for the voltage difference between ch0 + and ch0 C or ch1 + and ch1 C . note 9: the absolute voltage at ch0 + , ch0 C , ch1 + and ch1 C must be within this range. note 10: if less than 3ns is allowed, the output data will appear one clock cycle later. it is best for conv to rise half a clock before sck, when running the clock at rated speed. note 11: not the same as aperture delay. aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns conv to hold mode delay. note 12: the rising edge of sck is guaranteed to catch the data coming out into a storage latch. note 13: the time period for acquiring the input signal is started by the 32nd rising clock and it is ended by the rising edge of conv. note 14: the internal reference settles in 2ms after it wakes up from sleep mode with one or more cycles at sck and a 10 m f capacitive load. note 15: the full power bandwidth is the frequency where the output code swing drops by 3db with a 2.5v p-p input sine wave. note 16: maximum clock period guarantees analog performance during conversion. output data can be read with an arbitrarily long clock period. note 17: the ltc1407a is measured and specified with 14-bit resolution (1lsb = 152 m v) and the ltc1407 is measured and specified with 12-bit resolution (1lsb = 610 m v).
5 ltc1407/ltc1407a 1407f enobs and sinad vs input sinewave frequency snr vs input frequency v dd = 3v, t a = 25 c (ltc1407a) thd, 2nd and 3rd vs input frequency typical perfor a ce characteristics uw 748khz sine wave 4096 point fft plot 1403khz input summed with 1563khz input imd 4096 point fft plot 98khz sine wave 4096 point fft plot frequency (mhz) 0.1 10.0 enobs (bits) sinad (db) 11.0 12.0 1 10 100 1407 g01 9.0 9.5 10.5 11.5 8.5 8.0 62 68 74 56 59 65 71 53 50 frequency (mhz) 0.1 ?0 thd, 2nd, 3rd (db) ?4 ?8 ?2 ?6 1 10 100 1407 g02 ?6 ?2 ?8 ?04 ?0 ?4 thd 3rd 2nd frequency (mhz) 0.1 62 snr (db) 56 50 1 10 100 1407 g03 68 65 59 53 71 74 frequency (khz) magnitude (db) ?0 ?0 ?0 1407 g04 ?0 ?0 ?20 ?00 0 1.5msps ?0 ?0 ?0 ?0 ?10 0 200 400 100 300 600 500 700 frequency (khz) magnitude (db) ?0 ?0 ?0 1407 g05 ?0 ?0 ?20 ?00 0 ?0 ?0 ?0 ?0 ?10 0 200 400 100 300 600 500 700 1.5msps frequency (khz) 0 magnitude (db) ?0 ?0 ?0 1407 g06 ?0 ?0 ?20 200 400 100 300 600 500 700 ?00 0 ?0 ?0 ?0 ?0 ?10 1.5msps differential linearity for ch0 with internal 2.5v reference output code 0 ?.0 differential linearity (lsb) ?.8 ?.4 ?.2 0 1.0 0.4 4096 8192 1407 g15 ?.6 0.6 0.8 0.2 12288 16384 integral linearity end point fit for ch0 with internal 2.5v reference output code 0 ?.0 integral linearity (lsb) ?.6 0.8 0.4 0 2.0 0.8 4096 8192 1407 g16 ?.2 1.2 1.6 0.4 12288 16384 sfdr vs input frequency frequency (mhz) 0.1 68 sfdr (db) 56 44 1 10 100 1407 g19 80 74 62 50 86 92 98 104
6 ltc1407/ltc1407a 1407f differential linearity for ch1 with internal 2.5v reference output code 0 ?.0 differential linearity (lsb) ?.8 ?.4 ?.2 0 1.0 0.4 4096 8192 1407 g17 ?.6 0.6 0.8 0.2 12288 16384 integral linearity end point fit for ch1 with internal 2.5v reference output code 0 ?.0 integral linearity (lsb) ?.6 0.8 0.4 0 2.0 0.8 4096 8192 1407 g18 ?.2 1.2 1.6 0.4 12288 16384 pssr vs frequency simultaneous input steps at ch0 and ch1 from 25 w time (ns) 0 0.6 analog inputs (v) 0.2 0.6 1.0 1.4 20 3.0 1407 g10 0.2 10 5 25 15 30 1.8 2.2 2.6 ch0 ch1 frequency (hz) 110 ?0 psrr (db) ?5 ?0 ?5 ?0 100 1k 10k 100k 1m 1407 g11 ?5 ?0 ?5 ?0 ?5 full-scale signal frequency response cmrr vs frequency crosstalk vs frequency frequency (hz) 1m 10m 100m 1g ?8 amplitude (db) ?2 ? 0 1407 g07 ?4 ?0 ?6 6 12 frequency (hz) ?0 cmrr (db) ?0 0 ?00 ?0 ?0 100 1k 1407 g08 ?20 10k 100k 1m 10m 100m ch0 ch1 frequency (hz) ?0 crosstalk (db) ?0 ?0 ?0 ?0 ?0 ?0 100 1k 10k 100k 1m 10m 1407 g09 ?0 ch0 to ch1 ch1 to ch0 v dd = 3v, t a = 25 c (ltc1407a) typical perfor a ce characteristics uw v dd = 3v, t a = 25 c (ltc1407/ltc1407a)
7 ltc1407/ltc1407a 1407f uu u pi fu ctio s ch0 + (pin 1): noninverting channel 0. ch0 + operates fully differentially with respect to ch0 C with a 0v to 2.5v differential swing and a 0 to v dd absolute input range. ch0 C (pin 2): inverting channel 0. ch0 C operates fully differentially with respect to ch0 + with a C2.5v to 0v differential swing and a 0 to v dd absolute input range. v ref (pin 3): 2.5v internal reference. bypass to gnd and a solid analog ground plane with a 10 m f ceramic capacitor (or 10 m f tantalum in parallel with 0.1 m f ceramic). can be overdriven by an external reference voltage 3 2.55v and v dd . ch1 + (pin 4): noninverting channel 1. ch1 + operates fully differentially with respect to ch1 C with a 0v to 2.5v differential swing and a 0 to v dd absolute input range. ch1 C (pin 5): inverting channel 1. ch1 C operates fully differentially with respect to ch1 + with a C2.5v to 0v differential swing and a 0 to v dd absolute input range. gnd (pins 6, 11): ground and exposed pad. this single ground pin and the exposed pad must be tied directly to the solid ground plane under the part. keep in mind that analog signal currents and digital output signal currents flow through these connections. v dd (pin 7): 3v positive supply. this single power pin supplies 3v to the entire chip. bypass to gnd pin and solid analog ground plane with a 10 m f ceramic capacitor (or 10 m f tantalum) in parallel with 0.1 m f ceramic. keep in mind that internal analog currents and digital output signal currents flow through this pin. care should be taken to place the 0.1 m f bypass capacitor as close to pins 6 and 7 as possible. sdo (pin 8): three-state serial data output. each pair of output data words represent the two analog input chan- nels at the start of the previous conversion. sck (pin 9): external clock input. advances the conver- sion process and sequences the output data on the rising edge. one or more pulses wake from sleep. conv (pin 10): convert start. holds the two analog input signals and starts the conversion on the rising edge. two pulses with sck in fixed high or fixed low state starts nap mode. four or more pulses with sck in fixed high or fixed low state starts sleep mode. reference voltage vs v dd v dd (v) 2.4890 v ref (v) 2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 2.8 3.0 3.2 3.4 1407 g12 2.6 3.6 reference voltage vs load current load current (ma) 0.4 0.8 1.2 1.6 1407 g13 2.0 0.2 0 0.6 1.0 1.4 1.8 2.4890 v ref (v) 2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 v dd = 3v, t a = 25 c (ltc1407/ltc1407a) typical perfor a ce characteristics uw
8 ltc1407/ltc1407a 1407f block diagra w + 1 2 7 3 6 s & h + 4 5 s & h gnd 11 exposed pad v ref 10 f ch0 ch0 + ch1 ch1 + 3v 10 f ltc1407a 8 10 9 three- state serial output port mux 2.5v reference timing logic v dd sdo conv sck 1407a bd 3msps 14-bit adc 14-bit latch 14-bit latch
9 ltc1407/ltc1407a 1407f ltc1407 timing diagram sck conv internal s/h status sdo *bits marked ??after d0 should be ignored t 7 t 3 t 1 1 34 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26 27 28 29 30 31 32 33 34 1 t 2 t 6 t 8 t 10 t 9 t 9 t 8 t 4 t 5 t 8 sample hold hold hold hi-z hi-z hi-z t conv 12-bit data word 12-bit data word sdo represents the analog input from the previous conversion at ch1 t throughput 1407a td01 d11 d10 d8 d7 d6 d5 d4 d3 d2 d1 d0 x* x* d9 d11 d10 d8 d7 d6 d5 d4 d3 d2 d1 d0 x* x* d9 sample t acq sdo represents the analog input from the previous conversion at ch0 ltc1407a timing diagram sck conv internal s/h status sdo t 7 t 3 t 1 1 34 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26 27 28 29 30 31 32 33 34 1 t 2 t 6 t 8 t 10 t 9 t 9 t 8 t 4 t 5 t 8 sample hold hold hold hi-z hi-z hi-z t conv 14-bit data word 14-bit data word sdo represents the analog input from the previous conversion at ch1 t throughput 1407a td01 d13 d12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 d13 d12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 sample t acq sdo represents the analog input from the previous conversion at ch0 ti i g diagra s w u w
10 ltc1407/ltc1407a 1407f nap mode and sleep mode waveforms sck to sdo delay t 8 t 10 sck sdo 1407 td03 v ih v oh v ol t 9 sck sdo v ih 90% 10% sck conv nap sleep v ref t 1 t 12 t 1 note: nap and sleep are internal signals 1407 td02 ti i g diagra s w u w
11 ltc1407/ltc1407a 1407f linearview is a trademark of linear technology corporation. applicatio s i for atio wu uu driving the analog input the differential analog inputs of the ltc1407/ltc1407a are easy to drive. the inputs may be driven differentially or as a single-ended input (i.e., the ch0 C input is grounded). all four analog inputs of both differential analog input pairs, ch0 + with ch0 C and ch1 + with ch1 C , are sampled at the same instant. any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors at the end of conver- sion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1407/ltc1407a inputs can be driven directly. as source impedance increases, so will acquisition time. for minimum acquisition time with high source impedance, a buffer amplifier must be used. the main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). also keep in mind, while choosing an input amplifier, the amount of noise and harmonic distortion added by the amplifier. choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100 w ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small- signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1407/ltc1407a depends on the application. generally, applications fall into two categories: ac applications where dynamic specifications are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1407/ltc1407a. (more detailed informa- tion is available in the linear technology databooks and on the linearview tm cd-rom.) ltc1566-1: low noise 2.3mhz continuous time low- pass filter. lt ? 1630: dual 30mhz rail-to-rail voltage fb amplifier. 2.7v to 15v supplies. very high a vol , 500 m v offset and 520ns settling to 0.5lsb for a 4v swing. thd and noise are C 93db to 40khz and below 1lsb to 320khz (a v = 1, 2v p-p into 1k w , v s = 5v), making the part excellent for ac applications (to 1/3 nyquist) where rail-to-rail perfor- mance is desired. quad version is available as lt1631. lt1632: dual 45mhz rail-to-rail voltage fb amplifier. 2.7v to 15v supplies. very high a vol , 1.5mv offset and 400ns settling to 0.5lsb for a 4v swing. it is suitable for applications with a single 5v supply. thd and noise are C 93db to 40khz and below 1lsb to 800khz (a v = 1, 2v p-p into 1k w , v s = 5v), making the part excellent for ac applications where rail-to-rail performance is desired. quad version is available as lt1633. lt1801: 80mhz gbwp, C75dbc at 500khz, 2ma/ampli- fier, 8.5nv/ ? hz. lt1806/lt1807: 325mhz gbwp, C80dbc distortion at 5mhz, unity gain stable, rail-to-rail in and out, 10ma/amplifier, 3.5nv/ ? hz. lt1810: 180mhz gbwp, C90dbc distortion at 5mhz, unity gain stable, rail-to-rail in and out, 15ma/amplifier, 16nv/ ? hz.
12 ltc1407/ltc1407a 1407f lt1818/lt1819: 400mhz, 2500v/ m s, 9ma, single/dual voltage mode operational amplifier. lt6200: 165mhz gbwp, C85dbc distortion at 1mhz, unity gain stable, rail-to-rail in and out, 15ma/amplifier, 0.95nv/ ? hz. lt6203: 100mhz gbwp, C80dbc distortion at 1mhz, unity gain stable, rail-to-rail in and out, 3ma/amplifier, 1.9nv/ ? hz. lt6600: amplifier/filter differential in/out with 10mhz cutoff. input filtering and source impedance the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1407/ltc1407a noise and distortion. the small- signal bandwidth of the sample-and-hold circuit is 50mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog applicatio s i for atio wu uu inputs to minimize noise. a simple 1-pole rc filter is suf- ficient for many applications. for example, figure 1 shows a 47pf capacitor from cho + to ground and a 51 w source resistor to limit the net input bandwidth to 30mhz. the 47pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling-glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silvermica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from dam- age that may occur during soldering. metal film surface mount resistors are much less susceptible to both prob- lems. when high amplitude unwanted signals are close in frequency to the desired signal frequency a multiple pole filter is required. high external source resistance, combined with 13pf of input capacitance, will reduce the rated 50mhz input band- width and increase acquisition time beyond 39ns. figure 1. rc input filter ltc1407/ ltc1407a ch0 + ch0 v ref gnd 1407 f01 1 2 11 3 10 m f 47pf* 51 * ch1 + ch1 4 5 47pf* *tight tolerance required to avoid aperture skew degradation 51 * analog input analog input
13 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu input range the analog inputs of the ltc1407/ltc1407a may be driven fully differentially with a single supply. either input may swing up to 3v, provided the differential swing is no greater than 2.5v. in the valid input range, the noninvert- ing input of each channel should always be more positive than the inverting input of each channel. the 0v to 2.5v range is also ideally suited for single-ended input use with single supply applications. the common mode range of the inputs extend from ground to the supply voltage v dd . if the difference between the ch0 + and ch0 C inputs or the ch1 + and ch1 C inputs exceeds 2.5v, the output code will stay fixed at all ones, and if this difference goes below 0v, the ouput code will stay fixed at all zeros. internal reference the ltc1407/ltc1407a have an on-chip, temperature compensated, bandgap reference that is factory trimmed near 2.5v to obtain a precise 2.5v input span. the refer- ence amplifier output v ref , (pin 3) must be bypassed with a capacitor to ground. the reference amplifier is stable with capacitors of 1 m f or greater. for the best noise perfor- mance, a 10 m f ceramic or a 10 m f tantalum in parallel with a 0.1 m f ceramic is recommended. the v ref pin can be overdriven with an external reference as shown in figure 2. the voltage of the external reference must be higher than the 2.5v of the open-drain p-channel output of the internal reference. the recommended range for an external refer- ence is 2.55v to v dd . an external reference at 2.55v will see a dc quiescent load of 0.75ma and as much as 3ma during conversion. input span versus reference voltage the differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output v ref (pin 3) and the voltage at the exposed pad ground. the differential input range of adc is 0v to 2.5v when using the internal reference. the internal adc is referenced to these two nodes. this relationship also holds true with an external reference. differential inputs the adc will always convert the unipolar difference of ch0 + minus ch0 C or the unipolar difference of ch1 + minus ch1 C , independent of the common mode voltage at either set of inputs. the common mode rejection holds up at high frequencies (see figure 3.) the only requirement is that both inputs not go below ground or exceed v dd . figure 2 ltc1407/ ltc1407a v ref gnd 1407 f02 3 11 10 f 3v ref frequency (hz) ?0 cmrr (db) ?0 0 ?00 ?0 ?0 100 1k 1407 g08 ?20 10k 100k 1m 10m 100m ch0 ch1 figure 3. cmrr vs frequency
14 ltc1407/ltc1407a 1407f high quality tantalum and ceramic bypass capacitors should be used at the v dd and v ref pins as shown in the block diagram on the first page of this data sheet. for optimum performance, a 10 m f surface mount tantalum capacitor with a 0.1 m f ceramic is recommended for the v dd and v ref pins. alternatively, 10 m f ceramic chip capacitors such as x5r or x7r may be used. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. the v dd bypass ca- pacitor returns to gnd (pin 6) and the v ref bypass capaci- tor returns to the exposed pad ground (pin 11). care should be taken to place the 0.1 m f v dd bypass capacitor as close to pins 6 and 7 as possible. figure 5 shows the recommended system ground connec- tions. all analog circuitry grounds should be terminated at the ltc1407/ltc1407a exposed pad. the ground return from the ltc1407/ltc1407a pin 6 to the power supply should be low impedance for noise-free operation. the exposed pad of the 10-lead mse package is also tied to pin 6 and the ltc1407/ltc1407a gnd. the exposed pad should be soldered on the pc board to reduce ground connection inductance. digital circuitry grounds must be connected to the digital supply common. applicatio s i for atio wu uu integral nonlinearity errors (inl) and differential nonlin- earity errors (dnl) are largely independent of the common mode voltage. however, the offset error will vary. cmrr is typically better than 60db. figure 4 shows the ideal input/output characteristics for the ltc1407/ltc1407a. the code transitions occur mid- way between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is natural binary with 1lsb = 2.5v/16384 = 153 m v for the ltc1407a and 1lsb = 2.5v/4096 = 610 m v for the ltc1407. the ltc1407a has 1lsb rms of gaussian white noise. board layout and bypassing wire wrap boards are not recommended for high resolu- tion and/or high speed a/d converters. to obtain the best performance from the ltc1407/ltc1407a, a printed cir- cuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particu- lar, care should be taken not to run any digital track alongside an analog signal track. if optimum phase match between the inputs is desired, the length of the four input wires of the two input channels should be kept matched. but each pair of input wires to the two input channels should be kept separated by a ground trace to avoid high frequency crosstalk between channels. input voltage (v) unipolar output code 1407 f04 111...111 111...110 111...101 000...000 000...001 000...010 fs ?1lsb 0 figure 4. ltc1407/ltc1407a transfer characteristic
15 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu power-down modes upon power-up, the ltc1407/ltc1407a are initialized to the active state and is ready for conversion. the nap and sleep mode waveforms show the power down modes for the ltc1407/ltc1407a. the sck and conv inputs con- trol the power down modes (see timing diagrams). two rising edges at conv, without any intervening rising edges at sck, put the ltc1407/ltc1407a in nap mode and the power drain drops from 14mw to 6mw. the internal reference remains powered in nap mode. one or more rising edges at sck wake up the ltc1407/ltc1407a for service very quickly and conv can start an accurate conversion within a clock cycle. four rising edges at conv, without any intervening rising edges at sck, put the ltc1407/ltc1407a in sleep mode and the power drain drops from 14mw to 10 m w. one or more rising edges at sck wake up the ltc1407/ltc1407a for opera- tion. the internal reference (v ref ) takes 2ms to slew and settle with a 10 m f load. using sleep mode more frequently compromises the settled accuracy of the internal refer- ence. note that for slower conversion rates, the nap and sleep modes can be used for substantial reductions in power consumption. figure 5. recommended layout 1407 f05
16 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu digital interface the ltc1407/ltc1407a have a 3-wire spi (serial proto- col interface) interface. the sck and conv inputs and sdo output implement this interface. the sck and conv inputs accept swings from 3v logic and are ttl compat- ible, if the logic swing does not exceed v dd . a detailed description of the three serial port signals follows: conversion start input (conv) the rising edge of conv starts a conversion, but subse- quent rising edges at conv are ignored by the ltc1407/ ltc1407a until the following 32 sck rising edges have occurred. the duty cycle of conv can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. a simple approach to generate conv is to create a pulse that is one sck wide to drive the ltc1407/ltc1407a and then buffer this signal to drive the frame sync input of the processor serial port. it is good practice to drive the ltc1407/ltc1407a conv input first to avoid digital noise interference during the sample-to-hold transition trig- gered by conv at the start of conversion. it is also good practice to keep the width of the low portion of the conv signal greater than 15ns to avoid introducing glitches in the front end of the adc just before the sample-and-hold goes into hold mode at the rising edge of conv. minimizing jitter on the conv input in high speed applications where high amplitude sinewaves above 100khz are sampled, the conv signal must have as little jitter as possible (10ps or less). the square wave output of a common crystal clock module usually meets this requirement easily. the challenge is to generate a conv signal from this crystal clock without jitter corrup- tion from other digital circuits in the system. a clock divider and any gates in the signal path from the crystal clock to the conv input should not share the same integrated circuit with other parts of the system. as shown in the interface circuit examples, the sck and conv inputs should be driven first, with digital buffers used to drive the serial port interface. also note that the master clock in the dsp may already be corrupted with jitter, even if it comes directly from the dsp crystal. another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10mhz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40mhz). the jitter in these pll-generated high speed clocks can be several nanoseconds. note that if you choose to use the frame sync signal generated by the dsp port, this signal will have the same jitter of the dsps master clock. serial clock input (sck) the rising edge of sck advances the conversion process and also udpates each bit in the sdo data stream. after conv rises, the third rising edge of sck sends out two sets of 12/14 data bits, with the msb sent first. a simple approach is to generate sck to drive the ltc1407/ ltc1407a first and then buffer this signal with the appro- priate number of inverters to drive the serial clock input of the processor serial port. use the falling edge of the clock to latch data from the serial data output (sdo) into your processor serial port. the 14-bit serial data will be re- ceived right justified, in two 16-bit words with 32 or more clocks per frame sync. it is good practice to drive the ltc1407/ltc1407a sck input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. unlike the conv input, the sck input is not sensitive to jitter because the input signal is already sampled and held constant. serial data output (sdo) upon power-up, the sdo output is automatically reset to the high impedance state. the sdo output remains in high impedance until a new conversion is started. sdo sends out two sets of 12/14 bits in the output data stream after the third rising edge of sck after the start of conversion with the rising edge of conv. the two 12-/14-bit words are separated by two clock cycles in high impedance mode. please note the delay specification from sck to a valid sdo. sdo is always guaranteed to be valid by the next rising edge of sck. the 32-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors.
17 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu hardware interface to tms320c54x the ltc1407/ltc1407a are serial output adcs whose interface has been designed for high speed buffered serial ports in fast digital signal processors (dsps). figure 6 shows an example of this interface using a tms320c54x. the buffered serial port in the tms320c54x has direct access to a 2kb segment of memory. the adcs serial data can be collected in two alternating 1kb segments, in real time, at the full 3msps conversion rate of the ltc1407/ ltc1407a. the dsp assembly code sets frame sync mode at the bfsr pin to accept an external positive going pulse 1407 f06 7 10 9 8 6 3-wire serial interfacelink v dd conv sck ltc1407/ ltc1407a sdo v cc bfsr bclkr tms320c54x bdr gnd conv 0v to 3v logic swing clk 5v 3v b13 b12 figure 6. dsp serial interface to tms320c54x and the serial clock at the bclkr pin to accept an external positive edge clock. buffers near the ltc1407/ltc1407a may be added to drive long tracks to the dsp to prevent corruption of the signal to ltc1407/ltc1407a. this con- figuration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the dsp, may be needed to match the charac- teristic impedance of very long transmission lines. if you need to terminate the sdo transmission line, buffer it first with one or two 74acxx gates. the ttl threshold inputs of the dsp port respond properly to the 3v swing used with the ltc1407/ltc1407a.
18 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu ; 08-21-03 ****************************************************************** ; files: 1407asiab.asm -> 1407a sine wave collection with serial port interface ; both channels collected in sequence in the same 2k record ; bvectors.asm buffered mode. ; s2k14ini.asm 2k buffer size. ; unipolar mode ; works 16 or 64 clock frames. ; negative edge bclkr ; negative bfsr pulse ; -0 data shifted ; 1' cable from counter to conv at dut ; 2' cable from counter to clk at dut ; *************************************************************************** .width 160 .length 110 .title sineb0 bsp in auto buffer mode .mmregs .setsect .text, 0x500,0 ;set address of executable .setsect vectors, 0x180,0 ;set address of incoming 1407a data .setsect buffer, 0x800,0 ;set address of bsp buffer for clearing .setsect result, 0x1800,0 ;set address of result for clearing .text ;.text marks start of code start: ;this label seems necessary ;make sure /pwrdwn is low at j1-9 ;to turn off ac01 adc tim=#0fh prd=#0fh tcr = #10h ; stop timer tspc = #0h ; stop tdm serial port to ac01 pmst = #01a0h ; set up iptr. processor mode status register sp = #0700h ; init stack pointer. dp = #0 ; data page ar2 = #1800h ; pointer to computed receive buffer. ar3 = #0800h ; pointer to buffered serial port receive buffer ar4 = #0h ; reset record counter call sineinit ; double clutch the initialization to insure a proper sinepeek: call sineinit ; reset. the external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. wait goto wait ; buffered receive interrupt routine -- breceive: ifr = #10h ; clear interrupt flags tc = bitf(@bspce,#4000h) ; check which half (bspce(bit14)) of buffer if (ntc) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return_enable
19 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu ; mask and shift input data bufull: b = *ar3+ << -0 ; load acc b with bsp buffer and shift right -0 b = #07fffh & b ; mask out the tristate bits with #03fffh ; *ar2+ = data(#0bh) ; store b to out buffer and advance ar2 pointer tc = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h if (tc) goto start ; restart if out buffer is at 1fffh goto bufull ; dummy bsend return bsend return_enable ;this is also a dummy return to define bsend ;in vector table file bvectors.asm ; end isr .copy c:\dskplus\1407a\s2k14ini.asm ;initialize buffered serial port .space 16*32 ;clear a chunk at the end to mark the end ;====================================================================== ; ; vectors ; ;====================================================================== .sect vectors ;the vectors start here .copy c:\dskplus\1407a\bvectors.asm ;get bsp vectors .sect buffer ;set address of bsp buffer for clearing .space 16*0x800 .sect result ;set address of result for clearing .space 16*0x800 .end ; *************************************************************************** ; file: bvectors.asm -> vector table for the c54x dskplus 10.jul.96 ; bsp vectors and debugger vectors ; tdm vectors just return ; *************************************************************************** ; the vectors in this table can be configured for processing external and ; internal software interrupts. the dskplus debugger uses four interrupt ; vectors. these are reset, trap2, int2, and hpiint. ; * do not modify these four vectors if you plan to use the debugger * ; ; all other vector locations are free to use. when programming always be sure ; the hpiint bit is unmasked (imr=200h) to allow the communications kernel and ; host pc interact. int2 should normally be masked (imr(bit 2) = 0) so that the ; dsp will not interrupt itself during a hint. hint is tied to int2 externally. ; ; ;
20 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu .title vector table .mmregs reset goto #80h ;00; reset * do not modify if using debugger * nop nop nmi return_enable ;04; non-maskable external interrupt nop nop nop trap2 goto #88h ;08; trap2 * do not modify if using debugger * nop nop .space 52*16 ;0c-3f: vectors for software interrupts 18-30 int0 return_enable ;40; external interrupt int0 nop nop nop int1 return_enable ;44; external interrupt int1 nop nop nop int2 return_enable ;48; external interrupt int2 nop nop nop tint return_enable ;4c; internal timer interrupt nop nop nop brint goto breceive ;50; bsp receive interrupt nop nop nop bxint goto bsend ;54; bsp transmit interrupt nop nop nop trint return_enable ;58; tdm receive interrupt nop nop nop txint return_enable ;5c; tdm transmit interrupt nop nop int3 return_enable ;60; external interrupt int3 nop nop nop hpiint dgoto #0e4h ;64; hpiint * do not modify if using debugger * nop nop
21 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu .space 24*16 ;68-7f; reserved area ********************************************************************** * (c) copyright texas instruments, inc. 1996 * ********************************************************************** * * * file: bspi1407a.asm bsp initialization code for the c54x dskplus * * for use with 1407a in standard mode * * bspc and spc seem interchangeable in the c542 * * bspce and spce seem interchangeable in the c542 * ********************************************************************** .title buffered serial port initialization routine on .set 1 off .set !on yes .set 1 no .set !yes bit_8 .set 2 bit_10 .set 1 bit_12 .set 3 bit_16 .set 0 go .set 0x80 ********************************************************************** * this is an example of how to initialize the buffered serial port (bsp). * the bsp is initialized to require an external clk and fsx for * operation. the data format is 16-bits, burst mode, with autobuffering * enabled. set the variables listed below to configure the bsp for * your application. * ***************************************************************************************************** *ltc1407a timing with 40mhz crystal. * *10mhz, divided from 40mhz, forced to clkin by 1407a board. * *horizontal scale is 6.25ns/chr or 25ns period at bclkr * *bfsr pin j1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/ ~~~~~~~~~~~* *bclkr pin j1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/ ~\_/~\_/~* *bdr pin j1-26 ____ 22 ltc1407/ltc1407a 1407f applicatio s i for atio wu uu * 2' cable from counter to clk at dut *no right shift is needed to right justify the input data in the main program * *the two msbs should also be masked * **************************************************************************************************** * loopback .set no ;(digital looback mode?) dlb bit format .set bit_16 ;(data format? 16,12,10,8) fo bit intsync .set no ;(internal frame syncs generated?) txm bit intclk .set no ;(internal clks generated?) mcm bit burstmode .set yes ;(if burstmode=no, then continuous) fsm bit clkdiv .set 3 ;(3=default value, 1/4 clockout) pcm_mode .set no ;(turn on pcm mode?) fs_polarity .set yes ;(change polarity)yes=~~~\_/~~~, no=___/~\___ clk_polarity .set no ;(change polarity)for bclkr yes=_/~, no=~\_ frame_ignore .set !yes ;(inverted !yes -ignores frame) xmtautobuf .set no ;(transmit autobuffering) rcvautobuf .set no ;(receive autobuffering) xmthalt .set no ;(transmit buff halt if xmt buff is full) rcvhalt .set no ;(receive buff halt if rcv buff is full) xmtbufaddr .set 0x600 ;(address of transmit buffer) rcvbufaddr .set 0x800 ;(address of receive buffer) xmtbufsize .set 0x200 ;(length of transmit buffer) rcvbufsize .set 0x040 ;(length of receive buffer) * * see notes in the c54x cpu and peripherals reference guide on setting up * valid buffer start and length values. * * ********************************************************************** .eval ((loopback >> 1)|((format & 2)<<1)|(burstmode <<3)|(intclk <<4)|(intsync <<5)) ,spcval .eval ((clkdiv)|(fs_polarity <<5)|(clk_polarity<<6)|((format & 1)<<7)|(frame_ignore<<8)|(pcm_mode<<9)), spceval .eval (spceval|(xmtautobuf<<10)|(xmthalt<<12)|(rcvautobuf<<13)|(rcvhalt<<15)), spceval bspi1407a: bspc = #spcval ; places buffered serial port in reset bspce = #spceval ; programs bspce and abu axr = #xmtbufaddr ; initializes transmit buffer start address bkx = #xmtbufsize ; initializes transmit buffer size arr = #rcvbufaddr ; initializes receive buffer start address bkr = #rcvbufsize ; initializes receive buffer size bspc = #(spcval | go) ; bring buffered serial port out of reset return ; for transmit and receive because go=0xc0
23 ltc1407/ltc1407a 1407f u package descriptio mse package 10-lead plastic msop (reference ltc dwg # 05-08-1663) msop (mse) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 10 1 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc1407/ltc1407a 1407f lt/tp 1103 1k ? printed in usa ? linear technology corporation 2003 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments adcs ltc1608 16-bit, 500ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1609 16-bit, 250ksps serial adc 5v configurable bipolar/unipolar inputs ltc1403/ltc1403a 12-/14-bit, 2.8msps serial adc 3v, 15mw, msop package ltc1411 14-bit, 2.5msps parallel adc 5v, selectable spans, 80db sinad ltc1420 12-bit, 10msps parallel adc 5v, selectable spans, 72db sinad ltc1405 12-bit, 5msps parallel adc 5v, selectable spans, 115mw ltc1412 12-bit, 3msps parallel adc 5v supply, 2.5v span, 72db sinad ltc1402 12-bit, 2.2msps serial adc 5v or 5v supply, 4.096v or 2.5v span ltc1864/ltc1865 16-bit, 250ksps 1-/2-channel serial adcs 5v or 3v (l-version), micropower, msop package ltc1864l/ltc1865l dacs ltc1666/ltc1667 12-/14-/16-bit, 50msps dac 87db sfdr, 20ns settling time ltc1668 ltc1592 16-bit, serial softspan tm i out dac 1lsb inl/dnl, software selectable spans references lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.04% initial accuracy, 3ppm drift lt1460-2.5 micropower series voltage reference 0.10% initial accuracy, 10ppm drift softspan is a trademark of linear technology corporation.

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